QUARC serves as the dedicated training and learning hub for a group of eight talented doctoral candidates. Explore their research projects below
DC1: Architectural consideration on PQC accelerators based ARM processors
To investigate optimal (micro)-architectures to implement PQC accelerators for Crystal-Kyber, NTRU and Saber PQC quantum-resistant public key, signature and key encapsulation mechanism (KEM) system. To analyse the interdependence between hardware complexity and achievable reasonable size for the public key and investigate how to improve the security features of Crystal-Kyber, NTRU and Saber (lattice-based PQC).
DC2: Fast computing of PQC ciphers in GPUs on network interface cards
To investigate the implementation of FrodoKEM-972, NewHope-1024, and Kyber-1024 in a GPU embedded in a network interface card. To identify the latency savings in avoiding host GPUs, but rather a GPU acting as part of the networking fabric. In particular, speed up metric will be investigated and highlighted, including multiple parallel threads.
DC3: Co-integration of quantum communication with PQC key system
To evaluate the processing load when combining quantum communication processing for discrete variable (DV) or continuous variable (CV) quantum communications processing algorithms with PQC processing (cipher to be selected based on NIST standard to be published in 2022). To investigate whether a CPU or GPU processing approach provides acceptable curves capacity vs latency, in the content of line rate capacities (from Kbit/s to Gbit/s).
DC4: PQC for resilient communications against quantum computers
To select a NIST PQC standardized option (public-key encryption or digital signature) and its most intensive computing processing blocks in order to implement them on a HW accelerator (i.e. FPGA) or co-coprocessor for high-speed line-rate implementation (i.e. 25Gbit/s or 50Gbit/s). To transfer the algorithms of said blocks to IP cores as a reusable unit of logic/functionality and evaluate them in terms of latency and footprint.
DC5 : Edge computing offloading for PQC communication channels
To generate in a semi-symbolic math library (such as TensorFlow) a basic set of math operations from the PQC algorithm to implement the tensor operations extensions. To extend to GPU and FPGA offloading by including into GVirtus toolset the extensions, targeting PQC algorithms for utilization in edge computing environments. To investigate runtime time and mechanism to offload PQC processing to a higher tier processing unit vs locally.
DC6: PQC orchestrator for processing distribution
To investigate and implement a scheduling algorithm to identify and manage the utilization of the offloading processors for PQC. The scheduling algorithms (i.e. highest response ratio next, fixed-priority preemptive scheduling, etc..) will be defined and implemented based on aspects such as expected time to execute PQC operation, estimated run time of the operations (complexity), agree SLA parameters and required data availability.
DC7: PQC cipher architecture, optimization and integration
To investigate the cipher architecture of a PQC system and benchmark it against regular AES cryptography modules. To study and optimize the main building blocks of the PQC ciphers and integrate the extensions as part of a software development kit for programmable processing units.
DC8: Autonomous offloads in PQC systems
To investigate the introduction of autonomous offloads to PQC ciphers in order to reduce exposure to layer 5 or layer 4, and hence reduce or eliminate the offload dependence. To investigate strategies to copy out-of-sequence packets and to evaluate its impact on CPU utilization reduction.
More information on QUARC’s Doctoral Candidates
–Daniel Christian Lawo, Master of Science in Electrical Engineering and Information Technology and Bachelor of Science in Electrical Engineering and Information Technology, both from Technical University of Munich, Germany.
–Michał Podleś, Master Computer Science Artificial Intelligence and Data Analysis specialization, from AGH University of Science and Technology, Cracow, Poland.
–Abraham Cano Aguilera, Master of Science in Advanced Mathematics and Mathematical Engineering and Bachelor of Science in Telecommunication Engineering, both from Universitat Politécnica de Catalunya, Spain.
–Raphaël Frantz, Master of Science in High-Performance Visual Computing and Bachelor of Science in Computer Science both by the Université de Reims Champagne-Ardenne, Reims, France.
–Dimosthenis Iliadis-Apostolidis, Master of Engineering in Electrical and Computer Engineering, Aristotle University of Thessaloniki, Greece.
–Jerónimo Sánchez, Master of Science in High Performance Computing, Universidade da Coruña, Spain, and Bachelor of Science in Computer Science, Universidad de Almería, Spain.